Digital signal processors (DSPs) are well known in the art. DSPs are used for executing algorithms which in general have a "high content" of numerical operations. Examples of numerical operations include multiply, divide and accumulate (repeated summing). DSPs are used to process electrical signals using these "numerical operations" in, for example, communications as well as video processing applications.
A DSP is like a microprocessor in that it has a fetch unit which generates an address signal which is supplied to a memory the memory may be internal to the DSP chip or may be external thereto. The memory responds by supplying data signal along a data bus back to the DSP. The DSP then operates upon that data signal from the memory and can then store it back in the memory based upon the address generated by its fetch unit.
To increase the processing power of a DSP, prior an has suggested two approaches. The first approach is to simply increase the clock rate. However, increasing the clock rate or its frequency typically leads to high power consumption due to the oversize clock and logic drivers. Another prior art solution is to introduce some degree of parallel processing, such as pipeline processing. However, in pipeline processing, there is a limitation in that the signals operated thereon are not really operated upon simultaneously. They only to be operated upon simultaneously. In a typical pipeline operation, for example, if an operation required 4 clock cycles, a pipeline operation would start a first operation. After a delay of one clock cycle, i.e. without waiting for the complete processing of the first operation, a second operation is started. In this manner, once the pipeline is set up, four operations can be accomplished in four cycles. Pipeline has a drawback in that if a branch instruction should occur then the pipeline must be set up again before it can be processed. Other prior art techniques have included the use of multiple instances of processing data paths. This, however, leads to an input/output problem in that multiple data paths means that multiple data ports must be provided simultaneously. This requires high bandwidth memory access. Examples of prior art DSPs with pipeline operation include the TMS 320C25 or 320C5x, or 320C80, all available from Texas Instruments.
Hence, it is one object of the present invention to increase the parallel processing capability of a circuit and more particularly to a DSP incorporating such a circuit without the aforementioned drawbacks.